(24 pts.) The data path is given for a 4-bit multiplier. It consists of a 4-bit adder, a 4-bit register and a 9-bit shift register. The latter shifts right when its Sh input is asserted (assume that O's a entered at the left for this operation). A new value is loaded into the high-order 5 bits of the shift register when Ld is asserted. The same 5 bits are zeroed when Cl is asserted. These signals are synchronous. Design the control for a sequential 4-bit multiplier. 2. -bit Multiplier Sh ci shift right 4-bit Multiplicand Control -s Unit C1