2(a) [5 Marks] Write an equivalent VHDL process statement for the following selected signal assignment statement. with S select F <= A when "00", B when "01", C when "10", D when "11"; Q 2(b) [7 Marks] Draw the logic circuit that will be synthesized from the following VHDL model. If you change the order of the two signal assignments, what would be the synthesized circuit? library IEEE; use IEEE.STD LOGIC 1164.ALL; entity top is Port (clk, d: in STD LOGIC; q: out STD_LOGIC); end top; architecture q2c of top is begin signal sigl1 : std logic; P1: process (clk) begin if rising edge (clk) then sigl <= d; end q2c; q <= sigl; end if; end process