Question: Consider the truth table below. Design a simple VHDL entity and architecture that describe the outputs behavior. Use selected signal assignment conditional signal assignment (
Consider the truth table below. Design a simple VHDL entity and architecture that describe the outputs behavior. Use selected signal assignment conditional signal assignment (SELECT or CASE). What type of circuit is this? [10]
| A(2) | A(1) | A(0) | F(7) | F(6) | F(5) | F(4) | F(3) | F(2) | F(1) | F(0) |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
1.2 Write few lines of VHDL code that implements rotation of letters of one word. Lets say, a word has three letters, and you are asked to rotate them. Write down only PORT MAPPING part. [4]
1.3 Answer the following question regarding COMPONENT syntax: [6]
a. How many times does a component need to be declared within an architecture?
b. How many times can a component be instantiated?
a. Does declaring a component occur before or after the begin statement in the architecture?
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