2C

HD Webcam viewpoint of computer processing, explain the relationship between them. 4M Derive the expressions for speedup, efficiency and throughput of a k-stage linear pipeline processor in terms of the number of tasks n and the pipeline stages k. What is the speedup, efficiency and throughput as nz? 1B. 4M A processor is executing a program with P instructions. The ith instruction is a memory read instruction, the right-most N bits of which is a memory reference that contains the address of the operand to be read. With neat diagrams explain the data flow that take place in the processor to fetch the instruction and the operand for the i instruction execution IC. 2M Design a 4-stage linear pipelined floating point adder to add two floating point numbers A-a x 2P and B-bx 29. Write the operations performed in each stage. 2A. 3M 2B The routing functions of a Shuffle-Exchange network with N PEs are defined as follows: S(a a,a)aoa-... a1 Elan-1 a,a) an-1.... a,ao where an-1 ..alao is a PE address and n=log2 N Write the permutation cycles of both the routing functions and draw the recirculating M network for N-16 2C. What do you mean by masking schemes in SIMD array processor? Explain. Assume that an N N matrix is stored in SIMD processor such that column i is stored in the consecutive locations staring from address 100 in PEMi. What should be the global index register and local index register values to access each row and principal diagonal elements of the matrix? Briefly explain. Write the SIMD algorithm to find the sum of each column