$3$:$0569$

$45\%$

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RISC$-$V

RISC$-$V

$(43\%)$ Consider the design of the $5-$stage RISC$-$V pipeline shown below. Suppose we want to add a new R$-$type instruction to this design:

$(5\%)(5\%)(5\%)(8\%)(10\%)sltrd,rs1,rs2\frac{,}{\frac{?}{?}}$Reg$[rd]=1if$ Reg$[rs1]$

Its binary representation $isas$ follows. Note the $op$ code $is$ same $as$ add, sub, $or$ and and.

$\begin{array}{cc}0000000& rs2\\ rs1& 010\\ rd& 0110011\end{array}$

From Chapter $3,we$ also know that the ALU can support the set$-$less$-$than operation $by$ setting the ALUctr signals $to0111.$

$(a)(5\%)Dowe$ need $to$ add any new circuit blocks $or$ wires $to$ the design? Give your reasons.

$(b)(5\%)Dowe$ need $to$ make any change $to$ the main control "Control"? $(You$ need only describe your ideas. There $isno$ need $to$ show the truth table $or$ logic design.$)$

$(c)(5\%)Dowe$ need $to$ make any change $to$ the "ALU control"? $(You$ need only describe your ideas. There $isno$ need $to$ show the truth table $or$ logic design.$)$

$(d)(8\%)$ Suppose $we$ want $to$ stall the instruction $at$ the $EX$ stage and all the instructions following $it$ for one cycle and insert a "bubble" before $it.$ What should $wedoto$ the pipeline registers?

$(e)(5\%)$ Explain why setting the control signals $to0$ turns $an$ instruction into a NOP instruction?

$(f)(5\%)$ Suppose $we$ can only determine the outcome and target address $of$ a beq $at$ the $EX$ stage. How many "bubbles" $dowe$ need $to$ insert $to$ ensure correct execution when branch $is$ taken? Why?

$(g)(10\%)$ Suppose when the $IF$ stage tries $to$ fetch $an$ instruction from the instruction memory, $it$ encounters a $TLB$ miss and $an$ exception $is$ raised, how does the processor circuit work $to$ handle the exception? $(Note$ that the pipeline has two extra registers: SCAUSE and SEPC $to$ handle exceptions.$)$

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