$3)(10+18=28$ pts$)$ In DLX integer in$-$order pipeline with the forwarding technique discussed in class

while without the feature of $1/2-$cc read$/$write of registers,

a$)$ answer each of the following questions:

i$)$ If the PC increment process is still left at the $2$nd stage of the pipeline, what will be the ideal IPC?

ii$)$ How many total inputs are there to the MUX for the S$1$ input of the ALU? Where are they from?

iii$)$ What is the reason for having a separate path from the B buffer to SMDR$?$

iv$)$ If DLX requires $3$ clock cycles for the memory stage $($instead of one$),$ how many buffers are

needed at the output of ALU? Why specifically?

v$)$ What is the technique used to eliminate the WAW and WAR hazards?