$32-$bit Five Stage Pipeline MIPS Design and Implementation

Implement in Verilog the $5-$stage MIPS pipeline architecture discussed in class.

$32-$bit $5$ Stage Pipeline MIPS Design and Implementation

Implement in Verilog the $5-$stage MIPS pipeline architecture discussed in class.

Think of the simplest pipeline, then start adding additional features such as forwarding and hazard

detection units.