$3\mathrm{.}2$ The Up Mode

In the up mode, we set the upperbound of TAR to any value that we choose. TAR counts

from zero up to the value of register TACCR$0.$ This is the register of Channel $0.$ The up mode

is inherently linked to Channel $0.$ The timeline below shows how the timer runs. When TAR

reaches TACCR$0,$ it rolls back to zero and continues counting. Also, when TAR rolls back to

zero $($while counting$),$ the TAIFG flag is set by the hardware.

TAR: $0,1,2,...,$ TACCR$0,0,1,2,...,$ TACCR$0,0,1,...$

$$

TAIFG set TAIFG set

The register TACCR$0$ is $16-$bit. To have a period of $100$ cycles, we set TACCR$0=100-1=99.$

TAR then counts between $0$ and $99,$ spending one cycle at each count.

Since our microcontroller chip has multiple Timer A modules $($called Timer$0$ A$,$ Timer$1$ A$,$

etc$),$ we$$ll use the term TA$0$CCR$0$ in the code to indicate that we$$re using Timer$0$ A Channel $0$

register.

The code for the up mode is very similar to the continuous mode. Below are the differences.

First, we need to set TAR$$s upperbound using TA$0$CCR$0.$ Set it so the timer$$s period is $1$ second

$($flashing period is $2$ seconds$).$ We$$ll use ACLK $($configured to the $32$ KHz crystal$)$ and divide it

by $1.$