3. A given cache has 4-word cache lines, and the next level down in the memory hierarchy is implemented out of page-mode DRAMs with a latency to first word of 100ns, and a latency of 10ns for each additional sequential word accessed. Assume that 25 percent of all cache lines are dirty when they are evicted from the cache, and that the average dirty line was written to 5 times before it is evicted. (i) What is the average time to fetch a line into the cache if it is write-through? And what if it is Write-back? (ii) Would a write-back or write-through cache spend more time writing data to the next level of the memory? L a (5) (5)