3, A way-predicted cache modeled as 64 KB four-way set associative cache with 60% prediction accuracy and 0.007 misses per instruction for a certain workload. There are 0.25 data references per instruction. Assume that a mis predicted way access that hits in the cache takes three more cycles. Assume a cache miss takes 15 cycles and a cache hit time of 2 cycles. What is the average memory access time in cycles