$3.$ An Iterative Function $$Oops$!...$ I Did It Again$[40$ points$]$

Consider the iterative function

f$($x$)=$ a x $+$ b$,$

where a and b are fixed $8-$bit constants, and x is an $8-$bit register that is iteratively

updated according to

xnext $=$ a xcurrent $+$ b$.$

Example Iteration

Suppose a $=2,$ b $=3.$ Start with an initial $8-$bit value x $=5.$ Then the iteration

proceeds as follows $($in decimal just for illustration$)$:

x $=5$

x$=2*5+3=13$

x $=13$

x$=2*13+3=29$

x $=29$

x$=2*29+3=61$

x $=61$

x$=2*61+3=125$

x $=125$

x$=2*125+3=253$

x $=253$

x$=2*253+3=509($but in $8-$bit arithmetic, this wraps around!$)$

so

x$=509-256=253$

Once we reach values beyond the representable range of $8$ bits, the arithmetic wraps

around $($i$.$e$.$ it is computed modulo $256).$ Therefore, repeated iteration can generate

interesting results. In this particular example, the value x $=253$ becomes a fixed point

because further updates do not change x$.$

Problem

You have two $8-$bit constant inputs a $=$ a$0,...,$ a$7$ and b $=$ b$0,...,$ b$7,$ and an $8-$bit

variable register x $=$ x$0,...,$ x$7$ that you load externally. The goal is to iteratively

compute

x $=$ a $$ x $+$ b

on each clock cycle. If and when the circuit reaches a fixed point $($i$.$e$.$ xnext $=$ xcurrent$),$

it should set a Done signal to $1$ and place the final x value on an $8-$bit output Z$.$

In your design, you can use the following $$blocks$$ without specifying their internal

structure: D flip$-$flops, multiplexers, adder circuits, and a comparator circuit $($from

Homework $4).$ Specify everything else.

EE $2301,$ Fall $245$

$($a$)$ Multiplier Units. $[5$ points$]$

$$ Explain how to implement an $8-$bit unsigned multiplier for the product a$$x$.$

You may choose a simple shift$-$and$-$add design or a similar approach.

$($b$)8-$bit Iterative Update Unit.

$$ Design a combinational block that produces the new value of xnext $=$ a $$

xcurrent $+$ b from the present xcurrent.

$$ This block will contain an $8-$bit multiplier for a $$ x and an $8-$bit adder for

adding b$.$

$$ The output is an $8-$bit result xnext.

$($c$)$ Load Control.

$$ Use an $8-$bit register X to store the current x$,$ as well as two $8-$bit registers

for a and b$.$

$$ Show how X$,$ a$,$ and b are loaded when Load is $1.$

$($d$)$ Iteration Control.

$$ On each clock cycle $($with Load $=0),$ X is loaded with xnext.

$($e$)$ Stop Control.

$$ Show how Done is set to $1$ when xnext $=$ xcurrent $($i$.$e$.$ the iteration has reached

a fixed point$).$

For a problem like this, you must explain and annotate your circuit schematics, as well

as your simulation results. The grading will be somewhat subjective. If the grader

cannot understand your schematics or annotations, you will not get full points, even

if you can argue afterwards that the circuit works.