3) Answer these Verilog programming questions, be sure to answer all questions in each of a-e...

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3) Answer these Verilog programming questions, be sure to answer all questions in each of a-e below a. Evaluate these expressions to determine the value below assuming the initial value of out1 is 1'b1, assume x changes so that the always executes the begin end block. This is a blocking expression always @ (x) begin out1=1'b0; out2=out1; end out2 b. Evaluate these expressions to determine the value below assuming the initial value of out1 is 1'b1, assume x changes so that the always executes the begin end block. This is a nonblocking expression always @ (x) begin out1<=1'b0; out2<=out1; end out2 c. How do you need to change the port definition of this code to make this module compile correctly? module test(input A, B, output F); always @ (*) F = A|B; endmodule d. How does G need to be declared/defined to make this module compile? If you do not declare/define G what is the default? module test(input A, B, output F); always @ (*) G = A|B; assign F = G; endmodule 3) Answer these Verilog programming questions, be sure to answer all questions in each of a-e below a. Evaluate these expressions to determine the value below assuming the initial value of out1 is 1'b1, assume x changes so that the always executes the begin end block. This is a blocking expression always @ (x) begin out1=1'b0; out2=out1; end out2 b. Evaluate these expressions to determine the value below assuming the initial value of out1 is 1'b1, assume x changes so that the always executes the begin end block. This is a nonblocking expression always @ (x) begin out1<=1'b0; out2<=out1; end out2 c. How do you need to change the port definition of this code to make this module compile correctly? module test(input A, B, output F); always @ (*) F = A|B; endmodule d. How does G need to be declared/defined to make this module compile? If you do not declare/define G what is the default? module test(input A, B, output F); always @ (*) G = A|B; assign F = G; endmodule