3) Cache and DMA. The PIC32MZ data cache can be configured as either write-back or write-through, or turned off altogether. Since the DMA unit reads from and writes to physical memory and not the cache, how does this impact the program and the DMA? Specifically, a) If the data cache is configured for write-back, and a program writes some data to a buffer using KSEGO addresses that it wants to have sent out over a UART via DMA, what could actually be sent instead of what should have been sent? (Assume that the DMA is properly configured with the correct physical address of the buffer in its SSA register). b) Does this problem still exist if the cache is configured for write-through instead of write-back? Explain why or why not. c) If a program wants to receive some data via DMA to a buffer that it would then process using KSEGO addresses, what data could be processed? (Assume that the DMA is properly configured with the correct physical address of the buffer in its DSA register). d) Does you answer to part c depend on if the cache is configured for write-back or write though? Explain. e) Both KSEG1 and KSEGO point to the same physical memory. How does using KSEG1 addresses for the buffer solve each of the problems identified above? Indicate specifically how the problem in each case is solved. f) Noting that, by default, the xc32 compiler allocates data using KSEGO addresses, how might we access it instead using KSEG1 addresses? To answer this question assume that an integer is allocated using the C statement: unsigned int myint; give the code C needed to write a value to and read a value from myint using its KSEG1 address instead. Don't change the allocation statement in any way. (Another way to handle this is via adding a coherent attribute to the variable declaration. We will find out more about that later. Do not use that approach in this question.) 3) Cache and DMA. The PIC32MZ data cache can be configured as either write-back or write-through, or turned off altogether. Since the DMA unit reads from and writes to physical memory and not the cache, how does this impact the program and the DMA? Specifically, a) If the data cache is configured for write-back, and a program writes some data to a buffer using KSEGO addresses that it wants to have sent out over a UART via DMA, what could actually be sent instead of what should have been sent? (Assume that the DMA is properly configured with the correct physical address of the buffer in its SSA register). b) Does this problem still exist if the cache is configured for write-through instead of write-back? Explain why or why not. c) If a program wants to receive some data via DMA to a buffer that it would then process using KSEGO addresses, what data could be processed? (Assume that the DMA is properly configured with the correct physical address of the buffer in its DSA register). d) Does you answer to part c depend on if the cache is configured for write-back or write though? Explain. e) Both KSEG1 and KSEGO point to the same physical memory. How does using KSEG1 addresses for the buffer solve each of the problems identified above? Indicate specifically how the problem in each case is solved. f) Noting that, by default, the xc32 compiler allocates data using KSEGO addresses, how might we access it instead using KSEG1 addresses? To answer this question assume that an integer is allocated using the C statement: unsigned int myint; give the code C needed to write a value to and read a value from myint using its KSEG1 address instead. Don't change the allocation statement in any way. (Another way to handle this is via adding a coherent attribute to the variable declaration. We will find out more about that later. Do not use that approach in this question.)