Question: 3. Consider the following loop. LOOP: LDUR X10, [X1, #0] LDUR X11, [X1, #8] ADD X12, X10, X11 SUBI X1, X1, #16 CBNZ X12,

3. Consider the following loop. LOOP: LDUR X10, [X1, #0] LDUR X11, [X1, #8] ADD X12, X10, X11 SUBI X1, X1, #16 CBNZ X12, LOOP (10 points) Assume that perfect branch prediction is used (no stalls due to control hazards), that there are no delay slots, that the pipeline has full forwarding support, and that branches are resolved in the EX (as opposed to the ID) stage. 3.1 Show a pipeline execution diagram for the first two iterations of this loop.Give how many clock cycles it takes for 2 iterations of loop.

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