3. Considering the following state diagram for a 3-bits counter: 000 001 010 011 111 110...

 

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3. Considering the following state diagram for a 3-bits counter: 000 001 010 011 111 110 101 100 (a) Design the circuit using T flip-flops. (b) Using the Verilog modules we wrote in the sequential circuit's tutorial session, write a Verilog module for a T flip-flop with asynchronous reset. (c) Write a Verilog module and a test-bench for the counter circuit. 3. Considering the following state diagram for a 3-bits counter: 000 001 010 011 111 110 101 100 (a) Design the circuit using T flip-flops. (b) Using the Verilog modules we wrote in the sequential circuit's tutorial session, write a Verilog module for a T flip-flop with asynchronous reset. (c) Write a Verilog module and a test-bench for the counter circuit.

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