$3.$ Design a Combinational Logic$-$based Digital Lock System for secure access to a room or building. The system must: $$ Use a $4-$digit combination code that opens the lock when the correct combination is entered. $$ Use push$-$button switches $(0-9)$ for the user to enter their code. $$ Utilize only combinational logic $($AND$,$ OR$,$ NOT gates, multiplexers, decoders, etc.$)$ to control the lock mechanism. $$ Provide a feedback output $($e$.$g$.,$ Unlock signal$)$ when the correct code is entered, and a lock signal when the wrong code is entered. a$)$ Describe the key requirements of the Digital Lock System. What are the main functions of the system, and how can it be implemented using combinational logic? $(10$ marks$)$ b$)$ Identify and explain the system components required for the Digital Lock System. Specifically, mention the inputs, outputs, and logic gates that will be used. $(10$ marks$)$ c$)$ Assume the correct $4-$digit code for the digital lock system is $1101.$ Construct the truth table for the system, where the $4$ input digits are compared with the correct code. Clearly define the inputs and outputs of the truth table. $(12$ marks$)$ d$)$ From the truth table you created, write the Boolean expression for the 'Unlock' signal. Simplify the expression using Boolean algebra if necessary. $(12$ marks$)$ e$)$ Using the Boolean expression derived in the previous question, design the combinational logic circuit for the Digital Lock System. What logic gates will you use to implement the comparison of the entered code with the correct code? $(15$ marks$)$ f$)$ Describe how you would implement a "Lock" signal when the code is incorrect. Write the Boolean expression for the "Lock" signal and explain its relationship with the "Unlock" signal. $(12$ marks$)$ g$)$ How would you ensure the correct operation of the system when multiple button presses occur in quick succession? Would you need any additional components $($e$.$g$.,$ debouncing circuits$)?$ Explain your reasoning. $(10$ marks$)$ h$)$ Can you optimize the design by minimizing the number of logic gates required for the circuit? Explain if and how Boolean simplification techniques $($e$.$g$.,$ Karnaugh maps$)$ could be applied to reduce the circuit complexity. $(12$ marks$)$