3. Pass transistor logic (25pts) Consider the circuit shown in Fig. 1. Assume the inverter has balanced pull-up and pull-down strength. Neglect body effect, short channel effects and parasitic capacitance. VDD = 2.5V. Assume all transistors in this question have the same size and W=0.5um, L=0.25um. Use the following parameters. k' (A/V2) Vro (V) 0.43 -0.4 NMOS PMOS y (10.5) 0 0 Vpsat (V) 0.63 -1 1 (1-1) 0 115 x 10-6 -30 x 10-6 0 a) (5) What is the logic function implemented by this circuit? b) (5) Identify the input pattern that will cause non-zero static power dissipation (when subthreshold leakage is ignored) for the inverter when inputs A and B are stable. Explain the cause of this static power consumption. c) (8) Compute the static power consumption for the input pattern identified in part b). Ignore subthreshold leakage. c) (7) Show two possible solutions each with 1 additional transistor to avoid static power consumption. VOD B M2 Mat Out TE Mn2 Fig. 1 3. Pass transistor logic (25pts) Consider the circuit shown in Fig. 1. Assume the inverter has balanced pull-up and pull-down strength. Neglect body effect, short channel effects and parasitic capacitance. VDD = 2.5V. Assume all transistors in this question have the same size and W=0.5um, L=0.25um. Use the following parameters. k' (A/V2) Vro (V) 0.43 -0.4 NMOS PMOS y (10.5) 0 0 Vpsat (V) 0.63 -1 1 (1-1) 0 115 x 10-6 -30 x 10-6 0 a) (5) What is the logic function implemented by this circuit? b) (5) Identify the input pattern that will cause non-zero static power dissipation (when subthreshold leakage is ignored) for the inverter when inputs A and B are stable. Explain the cause of this static power consumption. c) (8) Compute the static power consumption for the input pattern identified in part b). Ignore subthreshold leakage. c) (7) Show two possible solutions each with 1 additional transistor to avoid static power consumption. VOD B M2 Mat Out TE Mn2 Fig. 1