Consider NMOS$-$based pass transistor logic with a level restorer implementing AND gate. The output inverter has equal width of PMOS and NMOS. The mobility of electron and holes are equal. If the NMOS pass transistors have width of $200$nm$,$ what is the maximum width of the level restorer for which the design will attain correct functionality. Assume that COX and L of NMOS and PMOS are equal. Use the following parameters. VDD $=1$V$.$ VTHN $=0\mathrm{.}3$V VTHP $=-0\mathrm{.}3$V VDSATN $=0\mathrm{.}3$V VDSATP $=-0\mathrm{.}3$V N $=0\mathrm{.}1$ V$-1$ P $=-0\mathrm{.}1$ V$-1($b$)$ Repeat part $($a$)$ if the width of the PMOS of the output inverter is changed to be twice that of the NMOS of the output inverter. $($c$)$ Explain the difference in your answers in $($a$)$ and $($b$)$