3. Q3 (12 marks) Direct-Mapped Caching For this question consider you have . Our addressable memory space starts at 0 A word size of 8 bytes a block size of 16 words A direct-mapped cache with 8 slots You are to simulate the state of your cache for the following memory accesses. You can assume before you begin the question the valid bit of each slot in your cache is set to false as nothing has been loaded in yet The order of accesses is: Block 0 Block 12 . Word 179 . Block -4 Word 195 Word at address 912 Word 73 . Block 17 . Block-4 Word 193 A) Provide a table that represents your cache, that shows the slot valid bit, tag, and the data within each slot of the cache after the entire series of accesses occurs. Whein displaying data, you can simply state which block of memory was loaded in B) How many cache misses occured in your sequence of accesses? Submit your answers in the file a3q3.txt XOR a3q3.pdf