$3.$ The circuit below is a $6$T SRAM cell. Let $\backslash ($ Q $\backslash )$ be initially high. The bit lines bit and $\backslash (\backslash$overline$\{$b i t$\}\backslash )$ are pre$-$charged to $\backslash ($ V$\_\{$D D$\}\backslash )$ and then left floating before a read or write operation.

$($a$)$ Describe the operation when the cell is read.

$($b$)$ Describe the operation when a $0$ is written to $\backslash ($ Q $\backslash ).$

$($c$)$ Between $\backslash ($ A$\_\{1\}\backslash )$ and $\backslash ($ P$\_\{1\}\backslash ),$ which transistor should be made stronger? Between $\backslash ($ A$\_\{1\}\backslash )$ and $\backslash ($ D$\_\{1\}\backslash ),$ which one should be stronger?

$($d$)$ Why two bit$-$lines $($bit and $\backslash (\backslash$overline$\{$b i t$\}\backslash ))$ are needed in one cell?

$($e$)$ Sketch an SRAM column schematic that allows the above write operation. You only need to draw one cell in the column for illustration.

$($f$)$ What is the main advantage of the $6$T SRAM cell compared to the case when the latch in $($a$)$ is used as a memory cell?