$3.$ Through SPICE simulation, calculate the setup, hold, and clock$-$to$-$Q times of a positive edgetriggered flip$-$flop. $(4$ points$)$ Here is inverter subcircuit : $.$include 'bsim.spice'

$*$ Define Power Supplies

VDD vdd $0$ dc $1\mathrm{.}8$

VSS vss $0$ dc $0$

$*$ Inverter Subcircuit Definition

$.$subckt inverter in out vdd vss

MN$1$ out in vss vss NFET L$=0\mathrm{.}18$u W$=0\mathrm{.}36$u

MP$1$ out in vdd vdd PFET L$=0\mathrm{.}18$u W$=0\mathrm{.}72$u

$.$ends inverter