Question: 3. Verilog code a) Write a behavioral model of J-K flip-flop with active-low asynchronous reset. b) Write a proper test-bench and stimulus, thoroughly test your

Verilog code

3. Verilog code a) Write a behavioral model of J-K flip-flop with

a) Write a behavioral model of J-K flip-flop with active-low asynchronous reset. b) Write a proper test-bench and stimulus, thoroughly test your J-K-Flip Flop. Also, show your waveform and describe why your JK-FF does what is is designed to do. a) Write a behavioral model of J-K flip-flop with active-low asynchronous reset. b) Write a proper test-bench and stimulus, thoroughly test your J-K-Flip Flop. Also, show your waveform and describe why your JK-FF does what is is designed to do

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