3.0 D Latches In a new project lab9step2 build a Gated D Latch using NAND gates and a NOT gate. Refer to Section 5.3 for a detailed explanation of D Latches. Figure 5.7a shows how to build a D Latch using NAND gates and a NOT gate. Once you have built the latch, label Cpr E 281 LAB 09 ELECTRICAL AND COMPUTER ENGINEERING OWA STATE UNIVERSITY Designing Latches and Flip-Flops the inputs Clk and D, and outputs Q and "Q. Use the DE2-115 board to observe the behavior of the latch. Since the pushbuttons can be a bit inconsistent it would be better to use a toggle switch to manually control the clock signal. (Recommend Clk-SWO, D-SW1, Q-LEDRO, O LEDG7). When you are convinced that the latch is performing as predicted, and you are confident you understand its behavior, complete the timing diagram on the answer sheet, (pulse your clock signal once with D low before you start), and demonstrate your circuit to the TA 3.0 D Latches In a new project lab9step2 build a Gated D Latch using NAND gates and a NOT gate. Refer to Section 5.3 for a detailed explanation of D Latches. Figure 5.7a shows how to build a D Latch using NAND gates and a NOT gate. Once you have built the latch, label Cpr E 281 LAB 09 ELECTRICAL AND COMPUTER ENGINEERING OWA STATE UNIVERSITY Designing Latches and Flip-Flops the inputs Clk and D, and outputs Q and "Q. Use the DE2-115 board to observe the behavior of the latch. Since the pushbuttons can be a bit inconsistent it would be better to use a toggle switch to manually control the clock signal. (Recommend Clk-SWO, D-SW1, Q-LEDRO, O LEDG7). When you are convinced that the latch is performing as predicted, and you are confident you understand its behavior, complete the timing diagram on the answer sheet, (pulse your clock signal once with D low before you start), and demonstrate your circuit to the TA