3.1 Prelab Begin by reading Sections 1, 2, and 3 above. Then answer the following questions. 3.1.1 Prelab Part 1: Load & Store Operations Data memory has two corresponding operations, Load and Store. In the load operation, an element from the data memory will be read and loaded to the register file, while in the store operation an element from the register file will be written to and stored into a location in the data memory. We have listed a sequence of tasks below which will implement an example of store and load operations. Go through them and answer the questions that follow: 1 2. 3. 4. reset Store values 2 and 4 to memory locations 1 and 2. Load the value of memory location 1 to reg 1. Invert the value of memory location 2 and put it in reg 2. Write 8'h15 to reg 3. Add reg 1 + reg 3 and store in reg 4. Store the contents of registers 3 and 4 to memory locations 3 and 4. Clear the regfile. 5 6. 7. 8. What would be the contents of the registers in the register file after the steps described in the file? Explain what these tests do functionally, (e.g. load Reg[1] from Mem[1], store value x in Mem[4] memory location, etc.) 3.1.2 Prelab Part 2: Create your Own Sequence! Write your own sequence of steps that tests the datapath using different values and different ALU instructions. What are the expected values in the registers after your test is complete? What ALU operations have you NOT tested? Explain what these tests do functionally, (e.g. load Reg[1] from Mem[1], store value x in Mem[4] memory location, etc.) Submit your Prelab responses with your report submission. 3.2 Entering Your Design Get the top level Verilog file, pdatapath_top.v from the course webpage. This Verilog code shows how all of your components are connected. You should use your regfile and alu from Lab 4. You will need to generate data memory and VIO to add to this experiment. Note that this VIO module has several new inputs and outputs. 3