3:104 cl" '5' E} B smu.instructure.com Question 20 What is the result of the below operation: 101110 - 1101 O 100001 0 110001 0 100101 0 100011 Quiz saved at 3:10pm 3:10 4 a smu.instructure.com O S = 1, R = 0 O S = 0, R =0 O S = 1, R =1 Question 17 1 pts On the edge of clock, D-FF change its state accordingly. O positive negative O zero O level Question 18 1 pts The inputs of first operation at D-FF reported Clk = 1 and D = 0. Second operation reported Clk = O and D = 0. What would be the output state (Q) at the second3:10 4 A smu.instructure.com negative O zero O level Question 18 1 pts The inputs of first operation at D-FF reported Clk = 1 and D = 0. Second operation reported Clk = O and D = 0. What would be the output state (Q) at the second operation? Memory O Reset O Set O Invalid D Question 19 1 pts What is the sum (in decimal) of below operation.3:10 7 a smu.instructure.com combinations? O NAND O AND O NOR O NOT Question 10 1 pts Logically, the output of a NAND gate would have the same Boolean expression as a(n): OR gate immediately followed by an inverter O AND gate immediately followed by an inverter O NOR gate immediately followed by an inverter O NOR gate immediately followed by an inverter D Question 11 1 pts3:10 4 smu.instructure.com O All inputs must be HIGH. O At least one input must be HIGH. At least one input must be LOW O All inputs are LOW Question 8 1 pts Logically, the output of a NOR gate would have the same Boolean expression as a(n): O NAND gate immediately followed by an inverter O OR gate immediately followed by an inverter O NOR gate immediately followed by an inverter O AND gate immediately followed by an inverter D Question 9 1 pts3:10 4 a smu.instructure.com O NOR, NAND, NOT O OR, AND, NAND O XOR, NOT, AND O XOR, AND and OR Question 16 1 pts What would be a "Set" state logic inputs for SR latch? O S = 0, R=1 O S = 1, R = 0 O S = 0, R =0 O S = 1, R =1 Question 17 1 pts On the edge of clock, D-FF change its state accordingly