3.11 Determine whether the following signal assignment is syntactically correct. If not, use the proper conversion function and type casting to correct the problem. library ieee; use ieee.std_logic.1164. all; use ieee .numeric std.all; signal s1, s2, s3, s4, s5, s6, s7: std.logic_vector (3 downto 0) signal u1, u2, u3, u4, u5, u6, u7: unsigned (3 downto 0); signal sg: signed (3 downto 0); u1 '1'); 68BASIC LANGUAGE CONSTRUCTS OF VHDL s2 s3 84 -1; s5 ,1'); s6