$[40$ points$]$ Assume that the processor has two$-$level of caches. The L$1$ hit latency is $1$ cycle;

the L$1$ hit rate is $80\%$; the L$2$ hit latency is $12$ cycles; the local hit rate of the L$2$ cache is

$60\%$; and the main memory access latency is $150$ cycles.

a$.$ What is the AMAT $($Average Memory Access Time$)?$ What is the average memory

stall cycle per instruction if every instruction generates $1\mathrm{.}3$ memory accesses on

average?

b$.$ Now assume that the $L3$ cache is added to improve the performance. The L$3$ hit

latency is $30$ cycles. If the $L3$ local hit rate is $45\%,$ what is the AMAT now? What

is the minimum $L3$ hit rate to make the $L3$ cache beneficial?