Question: 4 . 1 1 ) ( 4 . 1 0 in the 3 rd edition ) In parts f and g report what bank (

4.11)(4.10 in the 3rd edition) In parts f and g report what bank (a.k.a. row) the addressed
word is in and what the offset is within the bank.
Also note, this question asks you to re-do problem 4.10, and problem 4.10-part g has a typo.
It says to repeat exercise 9f, when what part g should actually say is repeat exercise 10f.
Redo exercise 10 assuming a 16M \times 16 memory built using 512K \times 8 RAM chips.
a) How many RAM chips are necessary?
b) If we were accessing one full word, how many chips would be involved?
c) How many address bits are needed for each RAM chip?
d) How many banks (rows) will this memory have?
e) How many address bits are needed for all memory?
f) If high-order interleaving is used, where would address 14(which is E in hex) be
located?
g) Repeat exercise 10f for low-order interleaving.

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