$4.(15$ points$)$ A student has designed the circuit in following figure to compute a registered four$-$input XOR function. The delay information is as follows:

$1.$ Each two$-$input XOR gate has a propagation delay of $100$ ps and a contamination delay of $55$ ps $.$

$2.$ Each flip$-$flop has a setup time of $60$ ps $,$ a hold time of $20$ ps $,$ a clock$-$to$-$Q maximum delay of $70$ ps $,$ and a clock$-$to$-$Q minimum delay of $50$ ps $.$

Your tasks are:

$($a$)(3$pt$)$ If there is no clock skew, what is the maximum operating frequency of the circuit?

$($b$)(3$pt$)$ How much clock skew can the circuit tolerate if it must operate at $2$ GHz $?$

$($c$)(3$pt$)$ How much clock skew can the circuit tolerate before it might experience a hold time violation?

$($d$)\backslash ((6\backslash$mathbf$\{$p t$\})\backslash )$ If we would like to redesign the combination logic circuit between the registers shown in the figure to make it faster and tolerate more clock skew, how can we do it by rearranging the three two$-$input XORs? What is its maximum frequency if there is no clock skew? How much clock skew can the circuit tolerate before it might experience a hold time violation?