$4\mathrm{.}2)$ Choose a coding scheme for the new instructions. Draw the different fields and specify their meaning. Try to minimize the Data$-$Path changes but still keep the minimal number of clock cycles required. It is recommended to use one of the regular types of instructions or some variation. Explain your choice.

$\backslash$table$[[3,3,2,2,2,2,2,2,2,2,2,2,1,1,1,1,1,1,1,1,1,1,9,8,7,6,5,4,3,2,1,0],[1,0,9,8,7,6,5,4,3,2,1,0,9,8,7,6,5,4,3,2,1,0,,,,,,,,,,],[,,,,,,,,,,,,,,,,,,,,,,]]$

$4\mathrm{.}3)($Complete on the drawing the missing connections needed to support the new instructions and the regular instructions as well in minimal number of clock cycles. $($Those are: add, sub, or$,$ and, xor, slt$,$ j$,$ beq, lw$,$ sw$).$ Add$/$change the original structure only if really needed. Explain your drawing. $($The priorities are: a$.$ Maximum speed, b$.$ Minimum additional $\frac{h}{w}).$

$4\mathrm{.}4)$ Did you need any new control signals? $($Additional signals that were not included in the original CPU$)$ If so$,$ name these signals and explain their function. Also specify usage of new combinations of existing control signals.

$4\mathrm{.}5)(3)$ Draw the entire state$-$diagram of the CPU with the new instructions $($including all the conditions required for switching from state to state$)$: