4. (20 pts) (a) (15 pts) A decoder dec2_4 is defined by the truth table Inputs outputs w w[0] y[3] y[2] y[1] y[0] 0 0 1 1 1 0 1 1 1 0 1 1 0 1 0 1 1 1 1 0 1 1 1 Write a Verilog file for module dec2_4 by using case statement 0 (b) (5pts) Assuming that your design is saved as dec2_4.v and that it has been successfully compiled and simulated. You are asked to demonstrate your design MyFPGA during class. Briefly and clearly describe the steps you are going to take. (10 points) Hint: you may create a top module testdec2_4 with Sw[1:0) as inputs and LEDR[3:0) as outputs if you choose a DE-series board or LED(3:0) on a Basys 3 board