4. (20 pts.) The following code is executed on a pipelined MIPS: outside: addi $s0, Szero, 100 addi $s4, Szero, 114 addi $80, $80, -4 lw $sl, 0 ($80) SW $sl, 100 ($80) addi $s2, $zero, 50 add $s2, $s2, 4 lw $s3, 500 ($s2) SW $s3, 700 ($s2) bne $s2, $s4, inside bne $50, Szero, outside inside: a) (5 pts.) What percentage of the instructions result in a flush if no branch prediction is implemented? Ignore all dependencies, stalls other than those caused by conditional branches, and pipeline fill start- up latency for the following questions: b) (5 pts.) What is the effective CPL if the branch logic is in the EX stage, and there is no branch prediction hardware? c) (5 pts.) What is the effective CPL if the branch logic is in the ID (Instruction Decode) stage with associated data forwarding, and there is no branch prediction hardware? d) (5 pts.) If 1-bit dynamic branch prediction is utilized with preset value of Predict-Taken, what is the branch prediction accuracy and the effective CPI for this code? Assume as in (c) that the branch logic is in the ID