$4-$bit Adder With Half and Full Adders$4-$bit Adder With Half and Full Adders

Using the following half adder that sums a and $b,$ ha module:

module ha$($ output $logicc,s,$ input $logica,b$;

and carry $(c,a,b$;

xor ${\displaystyle \underset{?}{\overset{?}{}}}(s,a,b)$;

endmodule

build the full adder using two ha modules and any other required gates. The ports for this module are:

module fa$($ output logic cout, s$,$ input logic a$,$ b$,$ cin $)$;

Use the full adder and half adder modules to build a $4-$bit adder module with the ports:

module add$4$bit$($output logic cout, output logic $[3$:$0]$ sum,

input logic $3$:$0$ a$,$ b$)$;

Behavourial $4-$bit Adder

Implement the add$4$bit adder using behavioural Verilog.

Using the following half adder that sums a and b$,$ ha module:

module ha$($ output logic c$,$ s$,$ input logic a$,$ b $)$;

and carry $($c$,$ a$,$ b$)$;

xor sum $($s$,$ a$,$ b$)$;

endmodule

build the full adder using two ha modules and any other required gates. The ports for this module are:

module fa$($ output logic cout, s$,$ input logic a$,$ b$,$ cin $)$;

Use the full adder and half adder modules to build a $4-$bit adder module with the ports:

module add$4$bit$($output logic cout, output logic $[3$:$0]$ sum,

input logic $[3$:$0]$ a$,$ b$)$;

please fix my code in verilog