4. Consider the following closed loop system with a proportional plus integral controller (block diagram given below). G(s)=(0.3s+1)1Gc(s)=(KP+sKI) (a) Using the root locus method, design the controller so that the maximum overshoot of the system is less than 5% and a settling time of 3 seconds or less. (b) Also compute the steady state error of the closed loop system with this controller for a unit ramp input (i.e. R(s)=1/s2 ). Desired Ch. Equation >s2+2zetawns+wn2=0 CLTF=1+GcG=0 1+Kp(s+Ki/Kp)/s(0.3s+1)=0 s2+(a)s+b=0