$4-$ Consider the following register$-$renamed code sequence executing on the microarchitecture shown below with

the following assumptions:

DADDI $IS,R2\frac{,}{b}ar(=),$

BIEZ $I4,$ Iocp

The ALUs can perform all arithmetic and branch operations, and the centralized Reservation Station $($RS$)$

can dispatch at most one instruction to each functional unit $($FU$)$ per cycle $($i$.$e$.,$ one instruction to each

ALU plus one instruction to the LD ST unit$).$

Dispatching instructions from RS to FUs requires one cycle and once instructions are in the FUs they have

the latencies shown below:

The front$-$end $($decoder and register renaming logic$)$ will continually supply two new instructions per clock

cycle to the RS$.$

At cycle $0,$ the first two register$-$renamed instructions of the code sequence are in the RS and dispatching is

performed.

There is no bypassing of results from FUs to dependent instructions, ie$.(1)$ results from FUs must be first

written to the RS at the end of cycle $t)$; $(2)$ the RS can dispatch dependent instructions to FUs at cycle $t+1,$

and $(3)$ instructions can execute at cycle $t+2.$

All FUs are fully pipelined.

$($a$)$ Show the content of the RS and clearly indicate which instruction$($s$)$ will be dispatched at each cycle. The

content of the RS for cycles $0$ and $1$ are shown below. The instructions in bold red indicate that they are

chosen to be dispatch to FUs in the next cycle.

$L.DT2,0(R2)$

$A.D.DI3,TH,I2$

Cycle $4$

Cycle $5$

Cycle $6$

Cycle $7$

$($b$)$ Show the cycle$-$by$-$cycle trace of how these instructions will execute in the FUs using the timing table shown

below. The execution of the first two instructions for cycles $1$ and $2$ are shown below.

$($c$)$ Suppose the assumption $(5)$ is changed so that bypassing of results from FUs to subsequent instructions is

possible, i$.$e$.,(1)$ results from FUs are written to the RS as well as bypassed $($forwarded$)$ to the dependent

instructions at the end of cycle $t,$ which means the dependent instructions can also start their execution at the

beginning of cycle $t+1.$ Repeat parts $($a$)$ and $($b$).$