4. Memory-Latency Wall [15 marks]

Killer micros mitigate memory latency by having a multilevel cache reduce

the latency to a couple of cycles, and then use pipeline parallelism (from

ILP) to mitigate the rest. This strategy would collapse if the cache left

any more than a few cycles of latency. Why? Because killer micros have

ridiculously little pipeline parallelism.

Let us calculate the average time 'tav' to complete a memory reference

measured in processor cycles. This will show the remaining latency.

Let 't_c' and 't_m' be the D-cache and DRAM access times, and let 'P' be the

probability of a D-cache hit. The cache line is 1-word long. We have:

tav = P * t_c + (1 - P) * (t_m + t_c) [in seconds]

= t_c + (1 - P) * t_m [in seconds]

= 1 + (1 - P) * t_m [in cycles ]

In line 3, we have assumed that 't_c' is always one cycle.

Assume a D-cache with a miss rate of 1%. Assume the DRAM latency decreases

by a factor of 1.03 every year, and the processor clock cycle decreases by a

factor of 1.75 every year. If a memory reference has a 200-cycle latency

today, how many cycles will 'tav' be after 6 years? after 8?