$4.$ You are to design a digital system, using the familiar control unit and datapath architecture, that receives some number of $8-$bit unsigned integers in through an $8-$bit data input port. The digital system is to determine and display in two separate $8-$bit data output ports, called MIN$2$ and MIN$3,$ the second and third smallest of the integers received so far. Duplicate data values are permitted in the input data stream, but the second and any further appearance of any particular data value will be ignored when determining the values of MIN$2$ and MIN$3.$ A third output data port, $16$ bits wide, will be used to display the total unsigned number DATA$\_$COUNT of data values received so far, with duplicate values contributing to the count.

Both the control unit and datapath are to share the same clock SYS$\_$CLK$.$ The rising edges of SYS$\_$CLK are to be used to latch all flip$-$flops and registers in the digital system design. Low$-$high$-$low synchronous pulses of a control input ENTER are used by an external system to enter the $8-$bit data values when ENTER $=\text{'}1\text{'}.$ Also to be provided is an asynchronous, active$-$low reset input RESETn.

In addition to the data output ports, there are also to be three output status bits, controlled by resettable flip$-$flops in the datapath, that function as follows:

$-$ Status output DATA$\_$RECEIVED is to be initialized to $\text{'}0\text{'}$ following a system reset. After at least one data value has been received, DATA$\_$RECEIVED is to change to $\text{'}1\text{'}$ and to stay at $\text{'}1\text{'}$ until the next system reset.

$-$ Status output VALID$\_$MIN$2$ is to be initialized to $\text{'}0\text{'}$ following a system reset. VALID$\_$MIN$2$ is to asserted to $\text{'}1\text{'}$ as soon as two distinct data values have been received through the input data port, and is to stay at $\text{'}1\text{'}$ until the next system reset.

$-$ Status output VALID$\_$MIN$3$ is to be initialized to $\text{'}0\text{'}$ following a system reset. VALID$\_$MIN$3$ is to asserted to $\text{'}1\text{'}$ as soon as three distinct data values have been received through the input data port, and is to stay at $\text{'}1\text{'}$ until the next system reset.

These requirements may still be incomplete. If you believe that some specification details are missing, then include those missing details and clearly justify your recommendation by stating how the intended requirements would be achieved with the new details added.

Your datapath design is to be expressed as a register transfer level $($RTL$)$ block diagram that specifies sufficient detail that the design could be readily encoded in structural$-$level VHDL$.$ The control unit is to be a Moore Machine that is fully specified as mnemonic$-$documented state $($MDS$)$ diagram that could be readily implemented in behavioural$-$level VHDL$.$ Provide a system$-$level block diagram that shows all of the external connections to the digital system as well as connections between the control unit and the datapath. VLDH code is not required in your anwer to this question. $[50$ marks$]$