4.3 When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off. In the following three problems, assume that we are starting with a datapath from Figure 4.2, where I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have latencies of 400ps, 100ps, 30ps, 120ps, 200ps, 350ps, and 100ps, respectively, and costs of 1000, 30, 10, 100, 200, 2000, and 500, respectively.

Consider the addition of a multiplier to the ALU. This addition will add 300ps to the latency of the ALU and will add a cost of 600 to the ALU. The result will be 5% fewer instructions executed since we will no longer need to emulate the MUL instruction.

Hints: Clock cycle time is determined by the critical path, which for the given latencies happens to be the load instruction: I-Mem (read instruction), Regs (takes longer than Control), Mux (select ALU input), ALU, Data Memory, and Mux (select value from memory to be written into Registers). The latency of this path is sum of latencies from all components on the path.

What is the clock cycle time (ps) without this improvement? (an integer only).

What is the new clock cycle time (ps) with this improvement? (an integer only).

What is the cost without this improvement? (an integer only).

What is the new cost with this improvement? (an integer only).

Does the improvement speed up the processor (Y/N)? (Answer either Y or N)