PLEASE REFER TO THE GRAPH BELOW TO ANSWER THE QUESTIONS

4.3 When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade from the following three problems assume that we are starting with a datapath have where Mux, ALU, Regs, em, and Control blocks latencies 400 ps, 100 ps, 30 ps, 120 ps, 200 ps, 350 ps, and 100 ps, ective and costs of 100, 200, 2000, and 500, respectively. of 1000, 30, 10, Consider the addition of multiplier to the ALU. This addition will add 300 ps to the latency of the ALU and will add a cost of 600 to the ALU. The result will be 5% fewer instructions executed since we will no longer need to emulate the MUL instruction. 4.3.1 [10] What is the cycle time with and without this improvement? clock 4.3.2 [10] What is the speedup achieved by adding this improvement