4-bit Comparator 2. 1. Write a VHDL code for a 4-bit comparator which takes two 4-bit input values and determines whether the numbers are equal. 2. 2. Write a structural VHDL code to implement the circuit of Fig. 2, using the components developed in 1.3(Write a behavioural code for a D ip- op in VHDL, with asynchronous reset and positive-edge-triggered clock. 1. 3. Write a structural VHDL code to implement the 4-bit ripple counter designed in 1.1 You must instantiate the D ip- ops created in 1.2.) and 2.1. 2. 3. Write a VHDL test bench for the above and verify by simulation. 2. 4. Implement the design in an FPGA (Note: You may need a `clock manager' to reduce the clock frequency).