$(50$ pts$)$ Dynamic Logic Design Given $\backslash (\backslash$mathrm$\{$F$\}=\backslash$mathrm$\{$AB$\}+\backslash$mathrm$\{$C$\}^\{\backslash$prime$\}+\backslash$mathrm$\{$E$\}\backslash )$ and assuming all the inputs and their complements are available, answer the following problems for function F :

a$)(10$ pts$)$ Design a domino circuit using one dynamic stage and one static stage.

b$)(10$ pts $)$ Design a domino circuit using $2$ dynamic stages and two static stages. Note: There is no unique solution to this part.

c$)(10$ pts$)$ Using the design of part $($a$)$ size the pull down network of the dynamic stage such that its current drive during evaluation is equal to that of an equivalent inverter with nMOS of size $($W$/$L$).$ Ignore the internal parasitics.

d$)(10$ pts$)$ Redo part $($c$)$ however assume the total internal capacitance seen at a drain or source terminal $($including diffusion and miller caps$)$ for a transistor of size W is C $.$ Also assume the external cap seen at the output of the dynamic stage is $5$ C $.$ Size the PDN of the dynamic stage progressively, such that the total W of the transistors in the PDN is less than $100$W$.$ Note: There is no unique solution to this part.

e$)(10$ pts$)$ Using your sizing of part $($e$)$ calculate the worst case Elmore delay of the dynamic stage during evaluation, assuming B is one of the inputs that is switching to $1.$