$5\mathrm{.}10\mathrm{.}3[5]$$$5\mathrm{.}4>$ Assuming a base CPI of $1\mathrm{.}0$ without any memory stalls, what is

the total CPI for P$1$ and P$2?$ Which processor is faster? $($When we say a "base CPI of

$1\mathrm{.}0",$ we mean that instructions complete in one cycle, unless either the instruction

access or the data access causes a cache miss.$)$

For the next three problems, we will consider the addition of an L$2$ cache to P$1($to

presumably make up for its limited L$1$ cache capacity$).$ Use the L$1$ cache capacities

and hit times from the previous table when solving these problems. The L$2$ miss

rate indicated is its local miss rate.

$5\mathrm{.}10\mathrm{.}4[10]$$$5\mathrm{.}4>$ What is the AMAT for P$1$ with the addition of an L$2$ cache?

Is the AMAT better or worse with the L$2$ cache?

$5\mathrm{.}10\mathrm{.}5[5]$$$5\mathrm{.}4>$ Assuming a base CPI of $1\mathrm{.}0$ without any memory stalls, what

is the total CPI for P$1$ with the addition of an $L2$ cache?

$5\mathrm{.}10\mathrm{.}6[10]$$$5\mathrm{.}4>$ What would the L$2$ miss rate need to be in order for P$1$ with

an L$2$ cache to be faster than P$1$ without an L$2$ cache?

$5\mathrm{.}10\mathrm{.}7[15]$$$5\mathrm{.}4>$ What would the $L2$ miss rate need to be in order for P$1$ with

an $L2$ cache to be faster than $P2$ without an $L2$ cache?

I need the solutions of $5\mathrm{.}10\mathrm{.}6$ and $5\mathrm{.}10\mathrm{.}7$ only