$5/15/10/10]<$ C$\mathrm{.}2>$ We begin with a computer implemented in single$-$cycle implementation. When the stages are split by functionality, the stages do not require exactly the same amount of time. The original machine had a clock cycle time of $7$ ns$.$ After the stages were split, the measured times were IF$,1$ ns; ID$,1\mathrm{.}5$ ns; EX$,1$ ns; MEM, $2$ ns; and WB$,1\mathrm{.}5$ ns$.$ The pipeline register delay is $0\mathrm{.}1$ ns$.$