$5\mathrm{.}17[$E$]$ During step $1$ of instruction processing, a memory Read operation is started to fetch an instruction at location $0$x$46000.$ However, as the instruction is not found in the cache, the Read operation is delayed, and the MFC signal does not become active until the fourth clock cycle. Assume that the delay is handled as described in Section $5\mathrm{.}6\mathrm{.}2.$ Show the contents of the PC during each of the four clock cycles of step $1,$ and also during step $2.$