$\frac{5}{75}$ Design a one$-$stage common emitter amplifier which meets the following specifications

Midband Gain $>35$ dB

Lower $3-$dB frequency, $f_L<mn>5</mn><mn>0</mn><mi>H</mi><mi>z</mi>$

Upper $3-$dB frequency, $f_H>500KHz$

Reasonable bias stability, $(1+)R_E>10R_B$

$R_s=100,R_C<mn>3</mn><mi>K</mi><mi></mi>$

Use the Circuit topology given in Figure PW$1.$ All specifications must be met while the amplifier is loaded by an oscilloscope probe as shown in the figure below. The coupling and bypass capacitors should be minimized. If you used any assumptions for the cut$-$off frequencies, state them clearly and justify them after your design.

There is more than one solution to this problem.

Design your amplifier with LT$-$Spice and take a printout of your design and results.

Comment on the relationship between the time constants corresponding to the dominant poles and the midband gain for the common emitter amplifier.

EE$313$ Analog Electronic Laboratory

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