$5\mathrm{.}7$ Consider the following program and cache behaviors.

Data Reads per

Data Writes per

$1000$ Instructions

$1000$ Instructions

$250$

$100$

Instruction Cache

Miss Rate

$0\mathrm{.}30\%$

Data Cache

Miss Rate

$2\%$

Block Size $($bytes$)$

$64$

$5\mathrm{.}7\mathrm{.}1[10]<$$$$5\mathrm{.}3,5\mathrm{.}8>$ Suppose a CPU with a write$-$through, write$-$allocate cache achieves a CPI of $2.$ What are the read and write bandwidths $($measured by bytes per cycle$)$ between RAM and the cache? $($Assume each miss generates a request for one block.$)$

$5\mathrm{.}7\mathrm{.}2[10]<$$$$5\mathrm{.}3,5\mathrm{.}8>$ For a write$-$back, write$-$allocate cache, assuming $30\%$ of replaced data cache blocks are dirty, what are the read and write bandwidths needed for a CPI of $2?$