Recall that we have two write policies and write allocation policies, and their combinations can be implemented either in L1 or L2 cache. Assume the following choices for L1 and L2 caches:

                           L1                                                                 L2________________

Write through, non-write allocate ..................... Write back, write allocate

1. Buffers are employed between different levels of memory hierarchy to reduce access latency. For this given configuration, list the possible buffers needed between L1 and L2 caches, as well as L2 cache and memory.

2. Describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block.

3. For a multilevel exclusive cache (a block can only reside in one of the L1 and L2 caches), configuration, describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block.

Consider the following program and cache behaviors.

4. For a write-through, write-allocate cache, what are the minimum read and write bandwidths (measured by byte per cycle) needed to achieve a CPI of 2?

5. For a write-back, write-allocate cache, assuming 30% of replaced data cache blocks are dirty, what are the minimal read and write bandwidths needed for a CPI of 2?

6. What are the minimal bandwidths needed to achieve the performance of CPI=1.5?

Data Reads per Data Writes per Instruction Cache Data Cache Block Size (byte) Miss Rate 1000 Instructions 1000 Instructions Miss Rate 100 250 0.30% 2% 64