5. a) For the code below, determine which access are likely to cause data cache misses. Next, insert prefetch instructions to reduce misses. Finally, calculate the number of prefect instructions executed and the misses avoided by prefecting. Lets assume we have an 32KB directed-mapped data cache with 32-byte blocks, and it is a write-back cache that does write allocate. The elements of a and b are 8 bytes long since they are double-precision floating-points arrays. There are 5 rows and 150 columns for a and 102 rows and 5 columns for b. Lets also assume they are not in the cache at the start of the program.

for (i=0; i <5; i=i+1)

for (j=0; j <150; j=j+1)

a[i][j] = b[j][0]*b[j+2][0];

b) Describe the following techniques for cache performance optimizations. 1) Critial word first and early restart. 2) Merging write buffer. Describe how each would affect hit time, miss rate and miss penalty.