5) Assume we have a pipelined MIPS implementation with the following base times: MEM 200ps EX IF 200ps ID 290ps WB 200ps 270ps 3 different version of the MIPS processor were designed with the following properties: I) No forwarding paths, no branch prediction. I) MEM/WB to ID/EX forwarding available with 30ps extra cost to MEM. I) EX/MEM to ID/EX forwarding available with 30ps extra cost to EX. 5) Assume we have a pipelined MIPS implementation with the following base times: MEM 200ps EX IF 200ps ID 290ps WB 200ps 270ps 3 different version of the MIPS processor were designed with the following properties: I) No forwarding paths, no branch prediction. I) MEM/WB to ID/EX forwarding available with 30ps extra cost to MEM. I) EX/MEM to ID/EX forwarding available with 30ps extra cost to EX