$(5$ points$)$ For the circuit below create a synthesizable verilog module using only the gate level

of abstraction$.$ Use the symbols on the schematic in the port list.

$(5$ points$)$ For the circuit below create a synthesizable verilog module using only the dataflow

level of abstraction$.$ In the port list declare all inputs and outputs using the vector format

$($Section $3\mathrm{.}2\mathrm{.}4$ in the text$).$

A $2-$to$-4$ decoder with output$-$polarity control.